1. Field of the Invention
This present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of using ion implantation techniques to control copper plating processes.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., memory cells, transistors, etc. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical semiconductor device to increase the overall speed of the device, as well as that of integrated circuit devices incorporating such semiconductor devices.
In modern integrated circuits, millions of very small semiconductor devices, e.g., transistors, memory cells, resistors, capacitors, etc., are formed above a semiconducting substrate, such as silicon. To produce a working integrated circuit, all of these various semi-conductor devices must be electrically coupled together. This is typically accomplished by a complex arrangement of conductive wiring, e.g., conductive lines and conductive plugs, that are formed in multiple layers of insulating material formed above the substrate. Historically, such conductive wiring patterns have been made from a variety of materials, such as aluminum.
However, as device dimensions continue to shrink, and as the desire for greater performance, e.g., faster operating speeds, has increased, copper has become more popular as the material for the conductive interconnections, i.e., conductive lines and vias, in modern integrated circuit devices. This is due primarily to the higher electrical conductivity of copper as compared to the electrical conductivity of other materials used for such wiring patterns, e.g., aluminum.
Typically, the copper wiring patterns may be formed by known techniques that involve single damascene or dual damascene processing techniques. FIGS. 1A–1C depict one illustrative process flow for forming conductive interconnections comprised of copper. As shown in FIG. 1A, a patterned layer of insulating material 12 is formed above a structure layer 10. The structure layer 10 is intended to be representative in nature in that it may be representative of a semiconducting substrate or a given level of a multiple level integrated circuit device. For example, the structure layer 10 may be a layer of insulating material, e.g., silicon dioxide, formed at some level above the substrate. Moreover, the structure layer 10 may, in some cases, have a plurality of conductive lines or vias (not shown in FIG. 1A) formed therein.
The patterned insulating layer 12 may be comprised of a variety of materials, e.g., silicon dioxide, BPSG, or a so-called “low-k” dielectric material, etc. The patterned insulating layer 12 may be formed by depositing the layer 12 and, thereafter, patterning the layer 12 using known photolithography and etching techniques. A plurality of trench features 14, 18 are thus defined in the patterned insulating layer 12. Ultimately, conductive interconnections comprised of copper will be formed in these trench features 14, 18. The features 14, 18 have a depth 19 of, for example, approximately 500 nm (5000 Å). Note that the width of the features 14, 18 may vary. For example, in the structure depicted in FIG. 1A, the features 14 have a width 16 of approximately 15 μm, whereas the feature 18 has a width 20 that is approximately 100 μm. That is, the physical dimensions of the features 14, 18 formed in the patterned layer of insulating material 12 may vary by a relatively large amount. For example, the features 14 may be used in forming conductive lines therein, and a large bond pad, e.g., approximately 100 μm×100 nm, may be formed in the feature 18. Ultimately, these various features 14, 18 will be filled with copper.
The process of forming the conductive interconnections comprised of copper typically begins with the conformal deposition of a barrier metal layer 22 above the patterned insulating layer 12, as depicted in FIG. 1B, which is an enlarged view of a portion of the patterned insulating layer 12. The various layers depicted in FIG. 1B are not shown in FIGS. 1A or 1C for purposes of clarity. After the barrier metal layer 22 is formed, a copper seed layer 24 is conformally deposited on the barrier metal layer 22. Next, known electroplating techniques are employed to form a bulk copper layer 26 (see FIG. 1A) above the patterned insulating layer 12 and in the features 14, 18. Thereafter, a chemical mechanical polishing process is performed to remove the excess copper material 26 positioned above the upper surface 13 of the patterned insulating layer 12. That is, the CMP process is performed until such time as the upper surface 27 of the copper conductive interconnections 26A is approximately planar with the upper surface 13 of the patterned layer of insulating material 12.
Due to the difference in sizes of the features 14, 18 in the patterned layer of insulating material 12, the features do not get completely filled at the same time. In the electroplating process, copper begins to uniformly form on the copper seed layer 24 across the wafer. Due to the large volume of the larger feature 18 as compared to the smaller volume of the smaller feature 14, it takes longer to fill the larger feature 18. Unfortunately, in existing processing methods, the electroplating process is performed for a sufficient duration to insure that the larger feature 18 is completely filled. A margin of error is also provided. For example, if the feature 18 has a depth of, for example, 500 nm, the electroplating process may be performed until such time as approximately 600 nm of copper has been formed in the feature 18. During this time, copper also continues to form in areas outside of the feature 18. This leads to an excessive accumulation of copper above portions of the patterned insulating layer 12 which must later be removed by expensive and time-consuming CMP processes. For example, in the process of filling the 500 nm deep feature 18, the copper above a portion of the patterned insulating layer 12 may be approximately 600 nm thick, as indicated by the arrow 17. This excess copper material tends to increase the time required for CMP operations, increase the cost of consumables used in CMP processes and otherwise reduce the efficiency of manufacturing operations.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.